SoC TEST SYSTEM SPEEDS DESIGN VERIFICATION CUTS TEST COST.

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  • Author(s): Bursky, Dave
  • Source:
    Electronic Design. 9/30/2002, Vol. 50 Issue 20, p43. 3p.
  • Additional Information
    • Subject Terms:
      ELECTRONIC circuit testers; ELECTRONIC circuit design; TESEDA Corp.
    • Abstract:
      Reports that on-chip test support logic and built-in self-test circuits have been developed to handle the design-for-test (DFT) methodologies for system-on-a-chip (SoC) designs. Teseda Corp.'s Validator 500 system which allows verification of the DFT structures in the SoCs; Focus on dc-scan testing; Ability of Validator to simplify and speed up the test preparation. INSET: P1500: The Standard For Embedded Test.