A design approach for class-AB operational amplifier using the gm/ID methodology.

The primary contribution of this paper is the extension of the gm/ID design methodology to two-stage operational amplifiers with class-AB output stages. First, the circuit is analyzed from the perspective of the gm/ID methodology, with a focus on its performance metrics and constraints. Second, to handle optimization targets and constraints automatically, the circuit sizing task is formulated as a single-objective optimization problem, and an optimizer is employed to obtain the temporary solution automatically. Benefiting from the gm/ID methodology, the gap between analytical equations and circuit simulation is highly reduced. Third, following the temporary solution, a guided fine-tuning method is introduced to further optimize the temporary solution. To demonstrate the effectiveness of this approach, we compared the equation-based method using the square-law model, two simulation-based methods and a commercial tool, Cadence ADE GXL, employing SMIC 55 nm and SMIC 180 nm CMOS technologies. The simulation results confirm the success of the proposed approach, showing that it not only reduces the gap between analytical equations and simulations, but also achieves the best performance metrics. [ABSTRACT FROM AUTHOR]

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