EDA start-up speeds design for small geometries.

A start-up EDA company claims to have addressed the problem of reaching design closure for very small geometries in reasonable time, by developing a routing tool that performs routing, extraction, analysis and optimization concurrently. Silicon Design Systems Inc. (SDS), which has a background in Asic design firm Silicon Value, said its K-Route tool helps to reduce manual post-layout design, which is the key time-consumer in modern chip design. K-Route, which is based on what SDS calls its adaptive fine-grained routing architecture, uses a common database for its microengines for extraction, timing, and signal integrity.