АНАЛІЗ АПАРАТНОЇ ПІДТРИМКИ КРИПТОГРАФІЇ У ПРИСТРОЯХ ІНТЕРНЕТУ РЕЧЕЙ (Ukrainian)

Analysis of hardware support of cryptography in Internet of Things-devices. (English)
Анализ аппаратной поддержки криптографии в устройствах Интернета вещей (Russian)

This article analyzes the features and functionality of embedded cryptographic accelerators in 8/16/32-bit general purpose microcontrollers designed to adapt traditional cryptography to the requirements of IoT-devices. It is established that traditional cryptographic algorithms and protocols used on the Internet in the case of software implementation do not meet the requirements of things related to –devices, the speed, the amount of memory required, and power consumption. The tendencies of development of light weight cryptography and cryptoaccelerators in microcontrollers from the point of view of balance of safety, cost and productivity are shown. The performance gain in the use of cryptographic accelerators for encryption, hashing and generation of random numbers in comparison with optimized software implementations is estimated. In particular, it is noted that the use of cryptographic accelerators allows to raise the speed of AES encryption 10-20 times for 8/16-bit processors and up to 150 times for 32-bit compared with software implementations of the algorithm. The growth of the SHA-1, SHA-256 hash rate algorithms in 32-bit microcontrollers is more than 100 times faster, and the НМАС is approaching 500. This allows 32-bit processors to use traditional cryptographic algorithms and protocols without significant constraints. It has also been shown that 32-bit microcontrollers have a trend towards the implementation of comprehensive security solutions that not only accelerate a wide range of symmetric and asymmetric algorithms and protocols, but also provide the ability to securely store and generate keys, securely download and update code, support digital signatures, and certificates. It is noted that manufacturers of microcontrollers are increasingly forced to pay attention to physical and algorithmic methods of protecting cryptographic accelerators from attacks through side-channels, in the first place attacks of analysis of power consumption, which constitute the main danger to devices of the Internet of things. [ABSTRACT FROM AUTHOR]

В данной статье проанализированы характеристики и функциональные возможности встроенных крипто- акселераторов в 8/16/32-битных микроконтроллерах общего назначения, призванных адаптировать традиционную криптографию к требованиям устройств Интернета вещей. Установлено, что традиционные криптоалгоритмы и протоколы, применяемые в сети Интернет при программной реализации не соответствуют требованиям, предъявляемым к устройствам Интернета вещей. Показано тенденции развития легковесной криптографии и криптоакселераторов в микроконтроллерах с точки зрения баланса безопасности, стоимости и производительности. Оценен выигрыш в производительности при применении криптоакселераторов для шифрования, хеширования и генерации случайных чисел по сравнению с оптимизированными программными реализациями. Обращается внимание на методы защиты криптоакселераторов от атак по побочным каналам, в первую очередь атак на энергопотребление, представляющих главную опасность. [ABSTRACT FROM AUTHOR]

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